1. Field of the Invention
The present invention relates to a semiconductor integrated circuit apparatus.
2. Related Art
There is a problem that variations among devices become larger as semiconductor devices become finer. If the variations become large, a circuit block which is very slow in operation appears with a certain probability. In circuit design conformed to delay time in worst case, it becomes difficult to quicken the clock frequency. Furthermore, large variations make estimation of delay times using simulation difficult and might cause a timing error due to a large delay which exceeds a predicted value. Furthermore, since the power supply voltage becomes low and the clock frequency becomes high because of device miniaturization and an increased degree of integration, the probability that a soft error will be caused by high energy particles is increasing.
As a conventional configuration of a flip-flop used to avoid the timing error or soft error, for example, a configuration described in U.S. Patent Application Publication No. 2004/0199821 is known. In this configuration, a different latch circuit is provided in parallel with a flip-flop on a pipeline. The latch circuit is used with a clock delayed a little from the system clock. Contents of data retained in the latch circuit and the flip-flop are compared with each other. If they are different from each other, an error is judged to be present and data correction is conducted.
In this method, however, there is a problem that the circuit area becomes large because another latch circuit is prepared and a comparison circuit for comparing data and a circuit for correcting data are used. There is also a problem that the power dissipation increases because the prepared latch circuit is brought into operation even if there are no errors.
A flip-flop configuration aiming at low power dissipation is disclosed in JP-A 2000-232339 (KOKAI) or JP-A 2004-56667 (KOKAI). Only when an input of a flip-flop is different from its output, an internal clock rises at rising timing of the clock. If the input is not different from the output, the internal clock does not rise. However, this configuration has no resistance against an unexpected error, because a decision is made only at the rising edge of the clock.